realtek: rtl838x: setup SDS entirely in PCS driver
authorJonas Jelonek <[email protected]>
Fri, 7 Nov 2025 16:15:17 +0000 (16:15 +0000)
committerHauke Mehrtens <[email protected]>
Mon, 8 Dec 2025 23:28:38 +0000 (00:28 +0100)
After having moved the configuration code and sequences from PHY and
DSA drivers to the PCS driver, add the hooks in PCS driver and remove
calls in PHY and DSA drivers to let PCS driver setup the SerDes
entirely on its own.

Also add pcs-handle to device tree definitions for most of the switch
ports because, due to the refactoring of the SerDes configuration, this
is needed now for all SerDes-attached ports.

Signed-off-by: Jonas Jelonek <[email protected]>
Link: https://github.com/openwrt/openwrt/pull/20876
Signed-off-by: Hauke Mehrtens <[email protected]>
25 files changed:
target/linux/realtek/dts/rtl8380_netgear_gs110tup-v1.dts
target/linux/realtek/dts/rtl8380_netgear_gs310tp-v1.dts
target/linux/realtek/dts/rtl8380_tplink_sg2xxx.dtsi
target/linux/realtek/dts/rtl8382_apresia_aplgs120gtss.dts
target/linux/realtek/dts/rtl8382_d-link_dgs-1210-16.dts
target/linux/realtek/dts/rtl8382_d-link_dgs-1210-20.dts
target/linux/realtek/dts/rtl8382_d-link_dgs-1210-26.dts
target/linux/realtek/dts/rtl8382_d-link_dgs-1210-28_common.dtsi
target/linux/realtek/dts/rtl8382_hpe_1920-16g.dts
target/linux/realtek/dts/rtl8382_hpe_1920-24g.dtsi
target/linux/realtek/dts/rtl8382_inaba_aml2-17gp.dts
target/linux/realtek/dts/rtl8382_iodata_bsh-g24mb.dts
target/linux/realtek/dts/rtl8382_panasonic_m16eg-pn28160k.dts
target/linux/realtek/dts/rtl8382_panasonic_m24eg-pn28240k.dts
target/linux/realtek/dts/rtl8382_tplink_t1600g-28ts-v3.dts
target/linux/realtek/dts/rtl8382_zyxel_gs1900-16-a1.dts
target/linux/realtek/dts/rtl8382_zyxel_gs1900-24-a1.dts
target/linux/realtek/dts/rtl8382_zyxel_gs1900-24e-a1.dts
target/linux/realtek/dts/rtl8382_zyxel_gs1900-24ep-a1.dts
target/linux/realtek/dts/rtl8382_zyxel_gs1900-24hp-a1.dts
target/linux/realtek/dts/rtl8382_zyxel_gs1900-24hp-b1.dts
target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/common.c
target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/dsa.c
target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c
target/linux/realtek/files-6.12/drivers/net/phy/rtl83xx-phy.c

index f34e9f7d96e0490bedbe86d57a052d4cf56e629e..b46aa57226bbfa33bf661504463afa6fbfdf04cf 100644 (file)
 &switch0 {
        ports {
                SWITCH_PORT(16, 9, qsgmii)
+
                /* TODO: fixed link SFP is not right */
-               SWITCH_SFP_PORT(24, 10, rgmii-id)
+               port24: port@24 {
+                       reg = <24>;
+                       label = SWITCH_PORT_LABEL(10);
+                       pcs-handle = <&serdes4>;
+                       phy-handle = <&phy24>;
+                       phy-mode = "1000base-x";
+                       fixed-link {
+                               speed = <1000>;
+                               full-duplex;
+                       };
+               };
        };
 };
index 5219e926ecd6d72c6438eaf1219e13c824b6a268..636046ed1b64676650a23f736c20ce0c2786e769 100644 (file)
 &switch0 {
        ports {
                /* TODO: fixed link SFP is not right */
-               SWITCH_SFP_PORT(24, 9, 1000base-x)
-               SWITCH_SFP_PORT(26, 10, 1000base-x)
+
+               port24: port@24 {
+                       reg = <24>;
+                       label = SWITCH_PORT_LABEL(9);
+                       pcs-handle = <&serdes4>;
+                       phy-handle = <&phy24>;
+                       phy-mode = "1000base-x";
+                       fixed-link {
+                               speed = <1000>;
+                               full-duplex;
+                       };
+               };
+               port26: port@26 {
+                       reg = <26>;
+                       label = SWITCH_PORT_LABEL(10);
+                       pcs-handle = <&serdes5>;
+                       phy-handle = <&phy26>;
+                       phy-mode = "1000base-x";
+                       fixed-link {
+                               speed = <1000>;
+                               full-duplex;
+                       };
+               };
        };
 };
index 7249d52275e78e693ba0d7793d3db16e2107f002..3854d5cf8b411d5a3d4d2299db786abd7b627aff 100644 (file)
                SWITCH_PORT(8, 8, internal)
 
                /* TODO: fixed link SFP is not right */
-               SWITCH_SFP_PORT(24, 9, 1000base-x)
-               SWITCH_SFP_PORT(26, 10, 1000base-x)
+               port24: port@24 {
+                       reg = <24>;
+                       label = SWITCH_PORT_LABEL(9);
+                       pcs-handle = <&serdes4>;
+                       phy-handle = <&phy24>;
+                       phy-mode = "1000base-x";
+                       fixed-link {
+                               speed = <1000>;
+                               full-duplex;
+                       };
+               };
+               port26: port@26 {
+                       reg = <26>;
+                       label = SWITCH_PORT_LABEL(10);
+                       pcs-handle = <&serdes5>;
+                       phy-handle = <&phy26>;
+                       phy-mode = "1000base-x";
+                       fixed-link {
+                               speed = <1000>;
+                               full-duplex;
+                       };
+               };
 
                port@28 {
                        ethernet = <&ethernet0>;
index 3d2adb27a44d027bcb2e2c5651068aee56a4bb4f..db14e7963be913a28b8e67c022956b1a3014ae55 100644 (file)
                #address-cells = <1>;
                #size-cells = <0>;
 
-               SWITCH_PORT(0, 1, qsgmii)
-               SWITCH_PORT(1, 2, qsgmii)
-               SWITCH_PORT(2, 3, qsgmii)
-               SWITCH_PORT(3, 4, qsgmii)
-               SWITCH_PORT(4, 5, qsgmii)
-               SWITCH_PORT(5, 6, qsgmii)
-               SWITCH_PORT(6, 7, qsgmii)
-               SWITCH_PORT(7, 8, qsgmii)
+               SWITCH_PORT_SDS(0, 1, 0, qsgmii)
+               SWITCH_PORT_SDS(1, 2, 0, qsgmii)
+               SWITCH_PORT_SDS(2, 3, 0, qsgmii)
+               SWITCH_PORT_SDS(3, 4, 0, qsgmii)
+               SWITCH_PORT_SDS(4, 5, 1, qsgmii)
+               SWITCH_PORT_SDS(5, 6, 1, qsgmii)
+               SWITCH_PORT_SDS(6, 7, 1, qsgmii)
+               SWITCH_PORT_SDS(7, 8, 1, qsgmii)
 
                SWITCH_PORT(8, 9, internal)
                SWITCH_PORT(9, 10, internal)
                SWITCH_PORT(14, 15, internal)
                SWITCH_PORT(15, 16, internal)
 
-               SWITCH_PORT(24, 17, qsgmii)
-               SWITCH_PORT(25, 18, qsgmii)
-               SWITCH_PORT(26, 19, qsgmii)
-               SWITCH_PORT(27, 20, qsgmii)
+               SWITCH_PORT_SDS(24, 17, 4, qsgmii)
+               SWITCH_PORT_SDS(25, 18, 4, qsgmii)
+               SWITCH_PORT_SDS(26, 19, 4, qsgmii)
+               SWITCH_PORT_SDS(27, 20, 4, qsgmii)
 
                port@28 {
                        ethernet = <&ethernet0>;
index 022902f356b540485671c72d00c74609fe14406a..1591ae349a15aae28df52c1d8ae931d57c9cb80c 100644 (file)
                #address-cells = <1>;
                #size-cells = <0>;
 
-               SWITCH_PORT(0, 1, qsgmii)
-               SWITCH_PORT(1, 2, qsgmii)
-               SWITCH_PORT(2, 3, qsgmii)
-               SWITCH_PORT(3, 4, qsgmii)
-               SWITCH_PORT(4, 5, qsgmii)
-               SWITCH_PORT(5, 6, qsgmii)
-               SWITCH_PORT(6, 7, qsgmii)
-               SWITCH_PORT(7, 8, qsgmii)
+               SWITCH_PORT_SDS(0, 1, 0, qsgmii)
+               SWITCH_PORT_SDS(1, 2, 0, qsgmii)
+               SWITCH_PORT_SDS(2, 3, 0, qsgmii)
+               SWITCH_PORT_SDS(3, 4, 0, qsgmii)
+               SWITCH_PORT_SDS(4, 5, 1, qsgmii)
+               SWITCH_PORT_SDS(5, 6, 1, qsgmii)
+               SWITCH_PORT_SDS(6, 7, 1, qsgmii)
+               SWITCH_PORT_SDS(7, 8, 1, qsgmii)
 
                SWITCH_PORT(8, 9, internal)
                SWITCH_PORT(9, 10, internal)
                SWITCH_PORT(14, 15, internal)
                SWITCH_PORT(15, 16, internal)
 
-               SWITCH_PORT(24, 17, qsgmii)
-               SWITCH_PORT(25, 18, qsgmii)
-               SWITCH_PORT(26, 19, qsgmii)
-               SWITCH_PORT(27, 20, qsgmii)
+               SWITCH_PORT_SDS(24, 17, 4, qsgmii)
+               SWITCH_PORT_SDS(25, 18, 4, qsgmii)
+               SWITCH_PORT_SDS(26, 19, 4, qsgmii)
+               SWITCH_PORT_SDS(27, 20, 4, qsgmii)
 
                port@28 {
                        ethernet = <&ethernet0>;
index 601d2980d6647741649ae220ada6136f6fd41887..0cf6ffb00cad338e61a2b32865ce24d6ba94fcff 100644 (file)
                #address-cells = <1>;
                #size-cells = <0>;
 
-               SWITCH_PORT(0, 1, qsgmii)
-               SWITCH_PORT(1, 2, qsgmii)
-               SWITCH_PORT(2, 3, qsgmii)
-               SWITCH_PORT(3, 4, qsgmii)
-               SWITCH_PORT(4, 5, qsgmii)
-               SWITCH_PORT(5, 6, qsgmii)
-               SWITCH_PORT(6, 7, qsgmii)
-               SWITCH_PORT(7, 8, qsgmii)
+               SWITCH_PORT_SDS(0, 1, 0, qsgmii)
+               SWITCH_PORT_SDS(1, 2, 0, qsgmii)
+               SWITCH_PORT_SDS(2, 3, 0, qsgmii)
+               SWITCH_PORT_SDS(3, 4, 0, qsgmii)
+               SWITCH_PORT_SDS(4, 5, 1, qsgmii)
+               SWITCH_PORT_SDS(5, 6, 1, qsgmii)
+               SWITCH_PORT_SDS(6, 7, 1, qsgmii)
+               SWITCH_PORT_SDS(7, 8, 1, qsgmii)
 
                SWITCH_PORT(8, 9, internal)
                SWITCH_PORT(9, 10, internal)
                SWITCH_PORT(14, 15, internal)
                SWITCH_PORT(15, 16, internal)
 
-               SWITCH_PORT(24, 17, qsgmii)
-               SWITCH_PORT(25, 18, qsgmii)
-               SWITCH_PORT(26, 19, qsgmii)
-               SWITCH_PORT(27, 20, qsgmii)
+               SWITCH_PORT_SDS(24, 17, 4, qsgmii)
+               SWITCH_PORT_SDS(25, 18, 4, qsgmii)
+               SWITCH_PORT_SDS(26, 19, 4, qsgmii)
+               SWITCH_PORT_SDS(27, 20, 4, qsgmii)
 
                port@28 {
                        ethernet = <&ethernet0>;
index 1102ae9424cfd25b3ad061ea05663807af4cafd3..34611e101e6961858b942c5284287ce5a8c8c263 100644 (file)
                #address-cells = <1>;
                #size-cells = <0>;
 
-               SWITCH_PORT(0, 1, qsgmii)
-               SWITCH_PORT(1, 2, qsgmii)
-               SWITCH_PORT(2, 3, qsgmii)
-               SWITCH_PORT(3, 4, qsgmii)
-               SWITCH_PORT(4, 5, qsgmii)
-               SWITCH_PORT(5, 6, qsgmii)
-               SWITCH_PORT(6, 7, qsgmii)
-               SWITCH_PORT(7, 8, qsgmii)
+               SWITCH_PORT_SDS(0, 1, 0, qsgmii)
+               SWITCH_PORT_SDS(1, 2, 0, qsgmii)
+               SWITCH_PORT_SDS(2, 3, 0, qsgmii)
+               SWITCH_PORT_SDS(3, 4, 0, qsgmii)
+               SWITCH_PORT_SDS(4, 5, 1, qsgmii)
+               SWITCH_PORT_SDS(5, 6, 1, qsgmii)
+               SWITCH_PORT_SDS(6, 7, 1, qsgmii)
+               SWITCH_PORT_SDS(7, 8, 1, qsgmii)
 
                SWITCH_PORT(8, 9, internal)
                SWITCH_PORT(9, 10, internal)
                SWITCH_PORT(14, 15, internal)
                SWITCH_PORT(15, 16, internal)
 
-               SWITCH_PORT(16, 17, qsgmii)
-               SWITCH_PORT(17, 18, qsgmii)
-               SWITCH_PORT(18, 19, qsgmii)
-               SWITCH_PORT(19, 20, qsgmii)
-               SWITCH_PORT(20, 21, qsgmii)
-               SWITCH_PORT(21, 22, qsgmii)
-               SWITCH_PORT(22, 23, qsgmii)
-               SWITCH_PORT(23, 24, qsgmii)
+               SWITCH_PORT_SDS(16, 17, 2, qsgmii)
+               SWITCH_PORT_SDS(17, 18, 2, qsgmii)
+               SWITCH_PORT_SDS(18, 19, 2, qsgmii)
+               SWITCH_PORT_SDS(19, 20, 2, qsgmii)
+               SWITCH_PORT_SDS(20, 21, 3, qsgmii)
+               SWITCH_PORT_SDS(21, 22, 3, qsgmii)
+               SWITCH_PORT_SDS(22, 23, 3, qsgmii)
+               SWITCH_PORT_SDS(23, 24, 3, qsgmii)
 
                port@24 {
                        reg = <24>;
index fe07078c2bfebffaa4bc8858affbe48b924c94dc..65e5646db4406e4f95d0a274cea941f45651236b 100644 (file)
                #address-cells = <1>;
                #size-cells = <0>;
 
-               SWITCH_PORT(0, 1, qsgmii)
-               SWITCH_PORT(1, 2, qsgmii)
-               SWITCH_PORT(2, 3, qsgmii)
-               SWITCH_PORT(3, 4, qsgmii)
-               SWITCH_PORT(4, 5, qsgmii)
-               SWITCH_PORT(5, 6, qsgmii)
-               SWITCH_PORT(6, 7, qsgmii)
-               SWITCH_PORT(7, 8, qsgmii)
+               SWITCH_PORT_SDS(0, 1, 0, qsgmii)
+               SWITCH_PORT_SDS(1, 2, 0, qsgmii)
+               SWITCH_PORT_SDS(2, 3, 0, qsgmii)
+               SWITCH_PORT_SDS(3, 4, 0, qsgmii)
+               SWITCH_PORT_SDS(4, 5, 1, qsgmii)
+               SWITCH_PORT_SDS(5, 6, 1, qsgmii)
+               SWITCH_PORT_SDS(6, 7, 1, qsgmii)
+               SWITCH_PORT_SDS(7, 8, 1, qsgmii)
 
                SWITCH_PORT(8, 9, internal)
                SWITCH_PORT(9, 10, internal)
                SWITCH_PORT(14, 15, internal)
                SWITCH_PORT(15, 16, internal)
 
-               SWITCH_PORT(16, 17, qsgmii)
-               SWITCH_PORT(17, 18, qsgmii)
-               SWITCH_PORT(18, 19, qsgmii)
-               SWITCH_PORT(19, 20, qsgmii)
-               SWITCH_PORT(20, 21, qsgmii)
-               SWITCH_PORT(21, 22, qsgmii)
-               SWITCH_PORT(22, 23, qsgmii)
-               SWITCH_PORT(23, 24, qsgmii)
+               SWITCH_PORT_SDS(16, 17, 2, qsgmii)
+               SWITCH_PORT_SDS(17, 18, 2, qsgmii)
+               SWITCH_PORT_SDS(18, 19, 2, qsgmii)
+               SWITCH_PORT_SDS(19, 20, 2, qsgmii)
+               SWITCH_PORT_SDS(20, 21, 3, qsgmii)
+               SWITCH_PORT_SDS(21, 22, 3, qsgmii)
+               SWITCH_PORT_SDS(22, 23, 3, qsgmii)
+               SWITCH_PORT_SDS(23, 24, 3, qsgmii)
 
-               SWITCH_PORT(24, 25, qsgmii)
-               SWITCH_PORT(25, 26, qsgmii)
-               SWITCH_PORT(26, 27, qsgmii)
-               SWITCH_PORT(27, 28, qsgmii)
+               SWITCH_PORT_SDS(24, 25, 4, qsgmii)
+               SWITCH_PORT_SDS(25, 26, 4, qsgmii)
+               SWITCH_PORT_SDS(26, 27, 4, qsgmii)
+               SWITCH_PORT_SDS(27, 28, 4, qsgmii)
 
                port@28 {
                        ethernet = <&ethernet0>;
index 59043b2f6f79948e0a69500243ec45e8e19caf0a..3e10cd62be4d9d943ec7203dcabd4cc86f32f948 100644 (file)
                SWITCH_PORT(14, 7, internal)
                SWITCH_PORT(15, 8, internal)
 
-               SWITCH_PORT(16, 9, qsgmii)
-               SWITCH_PORT(17, 10, qsgmii)
-               SWITCH_PORT(18, 11, qsgmii)
-               SWITCH_PORT(19, 12, qsgmii)
-               SWITCH_PORT(20, 13, qsgmii)
-               SWITCH_PORT(21, 14, qsgmii)
-               SWITCH_PORT(22, 15, qsgmii)
-               SWITCH_PORT(23, 16, qsgmii)
+               SWITCH_PORT_SDS(16, 9, 2, qsgmii)
+               SWITCH_PORT_SDS(17, 10, 2, qsgmii)
+               SWITCH_PORT_SDS(18, 11, 2, qsgmii)
+               SWITCH_PORT_SDS(19, 12, 2, qsgmii)
+               SWITCH_PORT_SDS(20, 13, 3, qsgmii)
+               SWITCH_PORT_SDS(21, 14, 3, qsgmii)
+               SWITCH_PORT_SDS(22, 15, 3, qsgmii)
+               SWITCH_PORT_SDS(23, 16, 3, qsgmii)
 
-               SWITCH_PORT(24, 17, qsgmii)
-               SWITCH_PORT(25, 18, qsgmii)
-               SWITCH_PORT(26, 19, qsgmii)
-               SWITCH_PORT(27, 20, qsgmii)
+               SWITCH_PORT_SDS(24, 17, 4, qsgmii)
+               SWITCH_PORT_SDS(25, 18, 4, qsgmii)
+               SWITCH_PORT_SDS(26, 19, 4, qsgmii)
+               SWITCH_PORT_SDS(27, 20, 4, qsgmii)
 
                port@28 {
                        ethernet = <&ethernet0>;
index 7358961943a594f41aed3c5a3e2961b7cf721048..a7cc555fa25997c0f24f7d670898e661613b20a5 100644 (file)
                #address-cells = <1>;
                #size-cells = <0>;
 
-               SWITCH_PORT(0, 1, qsgmii)
-               SWITCH_PORT(1, 2, qsgmii)
-               SWITCH_PORT(2, 3, qsgmii)
-               SWITCH_PORT(3, 4, qsgmii)
-               SWITCH_PORT(4, 5, qsgmii)
-               SWITCH_PORT(5, 6, qsgmii)
-               SWITCH_PORT(6, 7, qsgmii)
-               SWITCH_PORT(7, 8, qsgmii)
+               SWITCH_PORT_SDS(0, 1, 0, qsgmii)
+               SWITCH_PORT_SDS(1, 2, 0, qsgmii)
+               SWITCH_PORT_SDS(2, 3, 0, qsgmii)
+               SWITCH_PORT_SDS(3, 4, 0, qsgmii)
+               SWITCH_PORT_SDS(4, 5, 1, qsgmii)
+               SWITCH_PORT_SDS(5, 6, 1, qsgmii)
+               SWITCH_PORT_SDS(6, 7, 1, qsgmii)
+               SWITCH_PORT_SDS(7, 8, 1, qsgmii)
 
                SWITCH_PORT(8, 9, internal)
                SWITCH_PORT(9, 10, internal)
                SWITCH_PORT(14, 15, internal)
                SWITCH_PORT(15, 16, internal)
 
-               SWITCH_PORT(16, 17, qsgmii)
-               SWITCH_PORT(17, 18, qsgmii)
-               SWITCH_PORT(18, 19, qsgmii)
-               SWITCH_PORT(19, 20, qsgmii)
-               SWITCH_PORT(20, 21, qsgmii)
-               SWITCH_PORT(21, 22, qsgmii)
-               SWITCH_PORT(22, 23, qsgmii)
-               SWITCH_PORT(23, 24, qsgmii)
+               SWITCH_PORT_SDS(16, 17, 2, qsgmii)
+               SWITCH_PORT_SDS(17, 18, 2, qsgmii)
+               SWITCH_PORT_SDS(18, 19, 2, qsgmii)
+               SWITCH_PORT_SDS(19, 20, 2, qsgmii)
+               SWITCH_PORT_SDS(20, 21, 3, qsgmii)
+               SWITCH_PORT_SDS(21, 22, 3, qsgmii)
+               SWITCH_PORT_SDS(22, 23, 3, qsgmii)
+               SWITCH_PORT_SDS(23, 24, 3, qsgmii)
 
-               SWITCH_PORT(24, 25, qsgmii)
-               SWITCH_PORT(25, 26, qsgmii)
-               SWITCH_PORT(26, 27, qsgmii)
-               SWITCH_PORT(27, 28, qsgmii)
+               SWITCH_PORT_SDS(24, 25, 4, qsgmii)
+               SWITCH_PORT_SDS(25, 26, 4, qsgmii)
+               SWITCH_PORT_SDS(26, 27, 4, qsgmii)
+               SWITCH_PORT_SDS(27, 28, 4, qsgmii)
 
                port@28 {
                        ethernet = <&ethernet0>;
index c3683dc6a857450cc77eff8631c7c62d37053823..9d60abc1fda16bb46a6215b30e3d319be4f9b237 100644 (file)
                SWITCH_PORT(14, 7, internal)
                SWITCH_PORT(15, 8, internal)
 
-               SWITCH_PORT(16, 9, qsgmii)
-               SWITCH_PORT(17, 10, qsgmii)
-               SWITCH_PORT(18, 11, qsgmii)
-               SWITCH_PORT(19, 12, qsgmii)
-               SWITCH_PORT(20, 13, qsgmii)
-               SWITCH_PORT(21, 14, qsgmii)
-               SWITCH_PORT(22, 15, qsgmii)
-               SWITCH_PORT(23, 16, qsgmii)
+               SWITCH_PORT_SDS(16, 9, 2, qsgmii)
+               SWITCH_PORT_SDS(17, 10, 2, qsgmii)
+               SWITCH_PORT_SDS(18, 11, 2, qsgmii)
+               SWITCH_PORT_SDS(19, 12, 2, qsgmii)
+               SWITCH_PORT_SDS(20, 13, 3, qsgmii)
+               SWITCH_PORT_SDS(21, 14, 3, qsgmii)
+               SWITCH_PORT_SDS(22, 15, 3, qsgmii)
+               SWITCH_PORT_SDS(23, 16, 3, qsgmii)
 
                port@24 {
                        reg = <24>;
index b2dd2dff8c8b3c8313b41c14dfd2325dd110d642..4f2b209e800d45d0b8a9a8785b2c5d7a94af2f71 100644 (file)
                #address-cells = <1>;
                #size-cells = <0>;
 
-               SWITCH_PORT(0, 1, qsgmii)
-               SWITCH_PORT(1, 2, qsgmii)
-               SWITCH_PORT(2, 3, qsgmii)
-               SWITCH_PORT(3, 4, qsgmii)
-               SWITCH_PORT(4, 5, qsgmii)
-               SWITCH_PORT(5, 6, qsgmii)
-               SWITCH_PORT(6, 7, qsgmii)
-               SWITCH_PORT(7, 8, qsgmii)
+               SWITCH_PORT_SDS(0, 1, 0, qsgmii)
+               SWITCH_PORT_SDS(1, 2, 0, qsgmii)
+               SWITCH_PORT_SDS(2, 3, 0, qsgmii)
+               SWITCH_PORT_SDS(3, 4, 0, qsgmii)
+               SWITCH_PORT_SDS(4, 5, 1, qsgmii)
+               SWITCH_PORT_SDS(5, 6, 1, qsgmii)
+               SWITCH_PORT_SDS(6, 7, 1, qsgmii)
+               SWITCH_PORT_SDS(7, 8, 1, qsgmii)
 
                SWITCH_PORT(8, 9, internal)
                SWITCH_PORT(9, 10, internal)
                SWITCH_PORT(14, 15, internal)
                SWITCH_PORT(15, 16, internal)
 
-               SWITCH_PORT(16, 17, qsgmii)
-               SWITCH_PORT(17, 18, qsgmii)
-               SWITCH_PORT(18, 19, qsgmii)
-               SWITCH_PORT(19, 20, qsgmii)
-               SWITCH_PORT(20, 21, qsgmii)
-               SWITCH_PORT(21, 22, qsgmii)
-               SWITCH_PORT(22, 23, qsgmii)
-               SWITCH_PORT(23, 24, qsgmii)
+               SWITCH_PORT_SDS(16, 17, 2, qsgmii)
+               SWITCH_PORT_SDS(17, 18, 2, qsgmii)
+               SWITCH_PORT_SDS(18, 19, 2, qsgmii)
+               SWITCH_PORT_SDS(19, 20, 2, qsgmii)
+               SWITCH_PORT_SDS(20, 21, 3, qsgmii)
+               SWITCH_PORT_SDS(21, 22, 3, qsgmii)
+               SWITCH_PORT_SDS(22, 23, 3, qsgmii)
+               SWITCH_PORT_SDS(23, 24, 3, qsgmii)
 
                port@28 {
                        ethernet = <&ethernet0>;
index b2bc975722dd60a95be0ccf5aee217e44880e295..17ed20e0768bf8f9c102126012ab7166735042ce 100644 (file)
                SWITCH_PORT(14, 7, internal)
                SWITCH_PORT(15, 8, internal)
 
-               SWITCH_PORT(16, 9, qsgmii)
-               SWITCH_PORT(17, 10, qsgmii)
-               SWITCH_PORT(18, 11, qsgmii)
-               SWITCH_PORT(19, 12, qsgmii)
-               SWITCH_PORT(20, 13, qsgmii)
-               SWITCH_PORT(21, 14, qsgmii)
-               SWITCH_PORT(22, 15, qsgmii)
-               SWITCH_PORT(23, 16, qsgmii)
+               SWITCH_PORT_SDS(16, 9, 2, qsgmii)
+               SWITCH_PORT_SDS(17, 10, 2, qsgmii)
+               SWITCH_PORT_SDS(18, 11, 2, qsgmii)
+               SWITCH_PORT_SDS(19, 12, 2, qsgmii)
+               SWITCH_PORT_SDS(20, 13, 3, qsgmii)
+               SWITCH_PORT_SDS(21, 14, 3, qsgmii)
+               SWITCH_PORT_SDS(22, 15, 3, qsgmii)
+               SWITCH_PORT_SDS(23, 16, 3, qsgmii)
 
                port@28 {
                        ethernet = <&ethernet0>;
index 41df49f0aa83299da13cf9b97bee7b2b181bda95..ccd49ad3ca0f2550dcaaf94e4f30d303450a44f3 100644 (file)
                #address-cells = <1>;
                #size-cells = <0>;
 
-               SWITCH_PORT(0, 1, qsgmii)
-               SWITCH_PORT(1, 2, qsgmii)
-               SWITCH_PORT(2, 3, qsgmii)
-               SWITCH_PORT(3, 4, qsgmii)
-               SWITCH_PORT(4, 5, qsgmii)
-               SWITCH_PORT(5, 6, qsgmii)
-               SWITCH_PORT(6, 7, qsgmii)
-               SWITCH_PORT(7, 8, qsgmii)
+               SWITCH_PORT_SDS(0, 1, 0, qsgmii)
+               SWITCH_PORT_SDS(1, 2, 0, qsgmii)
+               SWITCH_PORT_SDS(2, 3, 0, qsgmii)
+               SWITCH_PORT_SDS(3, 4, 0, qsgmii)
+               SWITCH_PORT_SDS(4, 5, 1, qsgmii)
+               SWITCH_PORT_SDS(5, 6, 1, qsgmii)
+               SWITCH_PORT_SDS(6, 7, 1, qsgmii)
+               SWITCH_PORT_SDS(7, 8, 1, qsgmii)
 
                SWITCH_PORT(8, 9, internal)
                SWITCH_PORT(9, 10, internal)
                SWITCH_PORT(14, 15, internal)
                SWITCH_PORT(15, 16, internal)
 
-               SWITCH_PORT(16, 17, qsgmii)
-               SWITCH_PORT(17, 18, qsgmii)
-               SWITCH_PORT(18, 19, qsgmii)
-               SWITCH_PORT(19, 20, qsgmii)
-               SWITCH_PORT(20, 21, qsgmii)
-               SWITCH_PORT(21, 22, qsgmii)
-               SWITCH_PORT(22, 23, qsgmii)
-               SWITCH_PORT(23, 24, qsgmii)
+               SWITCH_PORT_SDS(16, 17, 2, qsgmii)
+               SWITCH_PORT_SDS(17, 18, 2, qsgmii)
+               SWITCH_PORT_SDS(18, 19, 2, qsgmii)
+               SWITCH_PORT_SDS(19, 20, 2, qsgmii)
+               SWITCH_PORT_SDS(20, 21, 3, qsgmii)
+               SWITCH_PORT_SDS(21, 22, 3, qsgmii)
+               SWITCH_PORT_SDS(22, 23, 3, qsgmii)
+               SWITCH_PORT_SDS(23, 24, 3, qsgmii)
 
                port@28 {
                        ethernet = <&ethernet0>;
index 20e0a868c694559d42e5fea80484445a08a58737..6bb0d807a88c4381873cfdff8aef93a84a810c22 100644 (file)
                #address-cells = <1>;
                #size-cells = <0>;
 
-               SWITCH_PORT(0, 1, qsgmii)
-               SWITCH_PORT(1, 2, qsgmii)
-               SWITCH_PORT(2, 3, qsgmii)
-               SWITCH_PORT(3, 4, qsgmii)
-               SWITCH_PORT(4, 5, qsgmii)
-               SWITCH_PORT(5, 6, qsgmii)
-               SWITCH_PORT(6, 7, qsgmii)
-               SWITCH_PORT(7, 8, qsgmii)
+               SWITCH_PORT_SDS(0, 1, 0, qsgmii)
+               SWITCH_PORT_SDS(1, 2, 0, qsgmii)
+               SWITCH_PORT_SDS(2, 3, 0, qsgmii)
+               SWITCH_PORT_SDS(3, 4, 0, qsgmii)
+               SWITCH_PORT_SDS(4, 5, 1, qsgmii)
+               SWITCH_PORT_SDS(5, 6, 1, qsgmii)
+               SWITCH_PORT_SDS(6, 7, 1, qsgmii)
+               SWITCH_PORT_SDS(7, 8, 1, qsgmii)
 
                SWITCH_PORT(8, 9, internal)
                SWITCH_PORT(9, 10, internal)
                SWITCH_PORT(14, 15, internal)
                SWITCH_PORT(15, 16, internal)
 
-               SWITCH_PORT(16, 17, qsgmii)
-               SWITCH_PORT(17, 18, qsgmii)
-               SWITCH_PORT(18, 19, qsgmii)
-               SWITCH_PORT(19, 20, qsgmii)
-               SWITCH_PORT(20, 21, qsgmii)
-               SWITCH_PORT(21, 22, qsgmii)
-               SWITCH_PORT(22, 23, qsgmii)
-               SWITCH_PORT(23, 24, qsgmii)
+               SWITCH_PORT_SDS(16, 17, 2, qsgmii)
+               SWITCH_PORT_SDS(17, 18, 2, qsgmii)
+               SWITCH_PORT_SDS(18, 19, 2, qsgmii)
+               SWITCH_PORT_SDS(19, 20, 2, qsgmii)
+               SWITCH_PORT_SDS(20, 21, 3, qsgmii)
+               SWITCH_PORT_SDS(21, 22, 3, qsgmii)
+               SWITCH_PORT_SDS(22, 23, 3, qsgmii)
+               SWITCH_PORT_SDS(23, 24, 3, qsgmii)
 
                port@28 {
                        ethernet = <&ethernet0>;
index 846ddce7773859188af9cd58e6bf834d5e01e1fa..4fe7a5938906f8f16ba1ddadfc72490a3124be17 100644 (file)
 
 &switch0 {
        ports {
-               SWITCH_PORT(16, 9, qsgmii)
-               SWITCH_PORT(17, 10, qsgmii)
-               SWITCH_PORT(18, 11, qsgmii)
-               SWITCH_PORT(19, 12, qsgmii)
-               SWITCH_PORT(20, 13, qsgmii)
-               SWITCH_PORT(21, 14, qsgmii)
-               SWITCH_PORT(22, 15, qsgmii)
-               SWITCH_PORT(23, 16, qsgmii)
+               SWITCH_PORT_SDS(16, 9, 2, qsgmii)
+               SWITCH_PORT_SDS(17, 10, 2, qsgmii)
+               SWITCH_PORT_SDS(18, 11, 2, qsgmii)
+               SWITCH_PORT_SDS(19, 12, 2, qsgmii)
+               SWITCH_PORT_SDS(20, 13, 3, qsgmii)
+               SWITCH_PORT_SDS(21, 14, 3, qsgmii)
+               SWITCH_PORT_SDS(22, 15, 3, qsgmii)
+               SWITCH_PORT_SDS(23, 16, 3, qsgmii)
        };
 };
 
index b83328b03c4635ec1de12696183c7605319e0fd0..63c96a88ae5b5e97d3fb56ca748e89fe175cf33a 100644 (file)
 
 &switch0 {
        ports {
-               SWITCH_PORT(0, 1, qsgmii)
-               SWITCH_PORT(1, 2, qsgmii)
-               SWITCH_PORT(2, 3, qsgmii)
-               SWITCH_PORT(3, 4, qsgmii)
-               SWITCH_PORT(4, 5, qsgmii)
-               SWITCH_PORT(5, 6, qsgmii)
-               SWITCH_PORT(6, 7, qsgmii)
-               SWITCH_PORT(7, 8, qsgmii)
+               SWITCH_PORT_SDS(0, 1, 0, qsgmii)
+               SWITCH_PORT_SDS(1, 2, 0, qsgmii)
+               SWITCH_PORT_SDS(2, 3, 0, qsgmii)
+               SWITCH_PORT_SDS(3, 4, 0, qsgmii)
+               SWITCH_PORT_SDS(4, 5, 1, qsgmii)
+               SWITCH_PORT_SDS(5, 6, 1, qsgmii)
+               SWITCH_PORT_SDS(6, 7, 1, qsgmii)
+               SWITCH_PORT_SDS(7, 8, 1, qsgmii)
 
                SWITCH_PORT(8, 9, internal)
                SWITCH_PORT(9, 10, internal)
                SWITCH_PORT(14, 15, internal)
                SWITCH_PORT(15, 16, internal)
 
-               SWITCH_PORT(16, 17, qsgmii)
-               SWITCH_PORT(17, 18, qsgmii)
-               SWITCH_PORT(18, 19, qsgmii)
-               SWITCH_PORT(19, 20, qsgmii)
-               SWITCH_PORT(20, 21, qsgmii)
-               SWITCH_PORT(21, 22, qsgmii)
-               SWITCH_PORT(22, 23, qsgmii)
-               SWITCH_PORT(23, 24, qsgmii)
+               SWITCH_PORT_SDS(16, 17, 2, qsgmii)
+               SWITCH_PORT_SDS(17, 18, 2, qsgmii)
+               SWITCH_PORT_SDS(18, 19, 2, qsgmii)
+               SWITCH_PORT_SDS(19, 20, 2, qsgmii)
+               SWITCH_PORT_SDS(20, 21, 3, qsgmii)
+               SWITCH_PORT_SDS(21, 22, 3, qsgmii)
+               SWITCH_PORT_SDS(22, 23, 3, qsgmii)
+               SWITCH_PORT_SDS(23, 24, 3, qsgmii)
 
                port@24 {
                        reg = <24>;
index 1f2a565d8124778163d0e45ab3d395015436ec62..c54648cc3205f39296334d558e0add664ba4fe14 100644 (file)
 
 &switch0 {
        ports {
-               SWITCH_PORT(1, 1, qsgmii)
-               SWITCH_PORT(0, 2, qsgmii)
-               SWITCH_PORT(3, 3, qsgmii)
-               SWITCH_PORT(2, 4, qsgmii)
-               SWITCH_PORT(5, 5, qsgmii)
-               SWITCH_PORT(4, 6, qsgmii)
-               SWITCH_PORT(7, 7, qsgmii)
-               SWITCH_PORT(6, 8, qsgmii)
+               SWITCH_PORT_SDS(1, 1, 0, qsgmii)
+               SWITCH_PORT_SDS(0, 2, 0, qsgmii)
+               SWITCH_PORT_SDS(3, 3, 0, qsgmii)
+               SWITCH_PORT_SDS(2, 4, 0, qsgmii)
+               SWITCH_PORT_SDS(5, 5, 1, qsgmii)
+               SWITCH_PORT_SDS(4, 6, 1, qsgmii)
+               SWITCH_PORT_SDS(7, 7, 1, qsgmii)
+               SWITCH_PORT_SDS(6, 8, 1, qsgmii)
 
                SWITCH_PORT(9, 9, internal)
                SWITCH_PORT(8, 10, internal)
                SWITCH_PORT(15, 15, internal)
                SWITCH_PORT(14, 16, internal)
 
-               SWITCH_PORT(17, 17, qsgmii)
-               SWITCH_PORT(16, 18, qsgmii)
-               SWITCH_PORT(19, 19, qsgmii)
-               SWITCH_PORT(18, 20, qsgmii)
-               SWITCH_PORT(21, 21, qsgmii)
-               SWITCH_PORT(20, 22, qsgmii)
-               SWITCH_PORT(23, 23, qsgmii)
-               SWITCH_PORT(22, 24, qsgmii)
+               SWITCH_PORT_SDS(17, 17, 2, qsgmii)
+               SWITCH_PORT_SDS(16, 18, 2, qsgmii)
+               SWITCH_PORT_SDS(19, 19, 2, qsgmii)
+               SWITCH_PORT_SDS(18, 20, 2, qsgmii)
+               SWITCH_PORT_SDS(21, 21, 3, qsgmii)
+               SWITCH_PORT_SDS(20, 22, 3, qsgmii)
+               SWITCH_PORT_SDS(23, 23, 3, qsgmii)
+               SWITCH_PORT_SDS(22, 24, 3, qsgmii)
        };
 };
 
index b4d07dd2d557f02b5c30cf1e1ff630b4e5c0d960..e3006d77a4af676db7c7cc9d09f6fa938afda0f3 100644 (file)
 
 &switch0 {
        ports {
-               SWITCH_PORT(0, 1, qsgmii)
-               SWITCH_PORT(1, 2, qsgmii)
-               SWITCH_PORT(2, 3, qsgmii)
-               SWITCH_PORT(3, 4, qsgmii)
-               SWITCH_PORT(4, 5, qsgmii)
-               SWITCH_PORT(5, 6, qsgmii)
-               SWITCH_PORT(6, 7, qsgmii)
-               SWITCH_PORT(7, 8, qsgmii)
+               SWITCH_PORT_SDS(0, 1, 0, qsgmii)
+               SWITCH_PORT_SDS(1, 2, 0, qsgmii)
+               SWITCH_PORT_SDS(2, 3, 0, qsgmii)
+               SWITCH_PORT_SDS(3, 4, 0, qsgmii)
+               SWITCH_PORT_SDS(4, 5, 1, qsgmii)
+               SWITCH_PORT_SDS(5, 6, 1, qsgmii)
+               SWITCH_PORT_SDS(6, 7, 1, qsgmii)
+               SWITCH_PORT_SDS(7, 8, 1, qsgmii)
 
                SWITCH_PORT(8, 9, internal)
                SWITCH_PORT(9, 10, internal)
                SWITCH_PORT(14, 15, internal)
                SWITCH_PORT(15, 16, internal)
 
-               SWITCH_PORT(16, 17, qsgmii)
-               SWITCH_PORT(17, 18, qsgmii)
-               SWITCH_PORT(18, 19, qsgmii)
-               SWITCH_PORT(19, 20, qsgmii)
-               SWITCH_PORT(20, 21, qsgmii)
-               SWITCH_PORT(21, 22, qsgmii)
-               SWITCH_PORT(22, 23, qsgmii)
-               SWITCH_PORT(23, 24, qsgmii)
+               SWITCH_PORT_SDS(16, 17, 2, qsgmii)
+               SWITCH_PORT_SDS(17, 18, 2, qsgmii)
+               SWITCH_PORT_SDS(18, 19, 2, qsgmii)
+               SWITCH_PORT_SDS(19, 20, 2, qsgmii)
+               SWITCH_PORT_SDS(20, 21, 3, qsgmii)
+               SWITCH_PORT_SDS(21, 22, 3, qsgmii)
+               SWITCH_PORT_SDS(22, 23, 3, qsgmii)
+               SWITCH_PORT_SDS(23, 24, 3, qsgmii)
        };
 };
index fb388e0a34e57a17c1b398429181b71e6c81fcea..8c8bc0b2bafbef46ee3f1225b0b3bb25d943dd22 100644 (file)
 
 &switch0 {
        ports {
-               SWITCH_PORT(0, 1, qsgmii)
-               SWITCH_PORT(1, 2, qsgmii)
-               SWITCH_PORT(2, 3, qsgmii)
-               SWITCH_PORT(3, 4, qsgmii)
-               SWITCH_PORT(4, 5, qsgmii)
-               SWITCH_PORT(5, 6, qsgmii)
-               SWITCH_PORT(6, 7, qsgmii)
-               SWITCH_PORT(7, 8, qsgmii)
+               SWITCH_PORT_SDS(0, 1, 0, qsgmii)
+               SWITCH_PORT_SDS(1, 2, 0, qsgmii)
+               SWITCH_PORT_SDS(2, 3, 0, qsgmii)
+               SWITCH_PORT_SDS(3, 4, 0, qsgmii)
+               SWITCH_PORT_SDS(4, 5, 1, qsgmii)
+               SWITCH_PORT_SDS(5, 6, 1, qsgmii)
+               SWITCH_PORT_SDS(6, 7, 1, qsgmii)
+               SWITCH_PORT_SDS(7, 8, 1, qsgmii)
 
                SWITCH_PORT(8, 9, internal)
                SWITCH_PORT(9, 10, internal)
                SWITCH_PORT(14, 15, internal)
                SWITCH_PORT(15, 16, internal)
 
-               SWITCH_PORT(16, 17, qsgmii)
-               SWITCH_PORT(17, 18, qsgmii)
-               SWITCH_PORT(18, 19, qsgmii)
-               SWITCH_PORT(19, 20, qsgmii)
-               SWITCH_PORT(20, 21, qsgmii)
-               SWITCH_PORT(21, 22, qsgmii)
-               SWITCH_PORT(22, 23, qsgmii)
-               SWITCH_PORT(23, 24, qsgmii)
+               SWITCH_PORT_SDS(16, 17, 2, qsgmii)
+               SWITCH_PORT_SDS(17, 18, 2, qsgmii)
+               SWITCH_PORT_SDS(18, 19, 2, qsgmii)
+               SWITCH_PORT_SDS(19, 20, 2, qsgmii)
+               SWITCH_PORT_SDS(20, 21, 3, qsgmii)
+               SWITCH_PORT_SDS(21, 22, 3, qsgmii)
+               SWITCH_PORT_SDS(22, 23, 3, qsgmii)
+               SWITCH_PORT_SDS(23, 24, 3, qsgmii)
 
                port@24 {
                        reg = <24>;
index fba5d0eb05470a727fed1ba675386c1c28203861..42f631316ceec586a4564a4fa4ab35df84e5d5e9 100644 (file)
 
 &switch0 {
        ports {
-               SWITCH_PORT(0, 1, qsgmii)
-               SWITCH_PORT(1, 2, qsgmii)
-               SWITCH_PORT(2, 3, qsgmii)
-               SWITCH_PORT(3, 4, qsgmii)
-               SWITCH_PORT(4, 5, qsgmii)
-               SWITCH_PORT(5, 6, qsgmii)
-               SWITCH_PORT(6, 7, qsgmii)
-               SWITCH_PORT(7, 8, qsgmii)
+               SWITCH_PORT_SDS(0, 1, 0, qsgmii)
+               SWITCH_PORT_SDS(1, 2, 0, qsgmii)
+               SWITCH_PORT_SDS(2, 3, 0, qsgmii)
+               SWITCH_PORT_SDS(3, 4, 0, qsgmii)
+               SWITCH_PORT_SDS(4, 5, 1, qsgmii)
+               SWITCH_PORT_SDS(5, 6, 1, qsgmii)
+               SWITCH_PORT_SDS(6, 7, 1, qsgmii)
+               SWITCH_PORT_SDS(7, 8, 1, qsgmii)
 
                SWITCH_PORT(8, 9, internal)
                SWITCH_PORT(9, 10, internal)
                SWITCH_PORT(14, 15, internal)
                SWITCH_PORT(15, 16, internal)
 
-               SWITCH_PORT(16, 17, qsgmii)
-               SWITCH_PORT(17, 18, qsgmii)
-               SWITCH_PORT(18, 19, qsgmii)
-               SWITCH_PORT(19, 20, qsgmii)
-               SWITCH_PORT(20, 21, qsgmii)
-               SWITCH_PORT(21, 22, qsgmii)
-               SWITCH_PORT(22, 23, qsgmii)
-               SWITCH_PORT(23, 24, qsgmii)
+               SWITCH_PORT_SDS(16, 17, 2, qsgmii)
+               SWITCH_PORT_SDS(17, 18, 2, qsgmii)
+               SWITCH_PORT_SDS(18, 19, 2, qsgmii)
+               SWITCH_PORT_SDS(19, 20, 2, qsgmii)
+               SWITCH_PORT_SDS(20, 21, 3, qsgmii)
+               SWITCH_PORT_SDS(21, 22, 3, qsgmii)
+               SWITCH_PORT_SDS(22, 23, 3, qsgmii)
+               SWITCH_PORT_SDS(23, 24, 3, qsgmii)
 
 
                port@24 {
index 6115c48f301cbc48418b4327f4d0756c8137fd82..52a6dd7345b17324b19007ba2c51139e8999df1a 100644 (file)
@@ -408,13 +408,6 @@ static int __init rtl83xx_mdio_probe(struct rtl838x_switch_priv *priv)
                sw_w32_mask(BIT(7), 0, RTL839X_SMI_GLB_CTRL);
        }
 
-       /* Power on fibre ports and reset them if necessary */
-       if (priv->ports[24].phy == PHY_RTL838X_SDS) {
-               pr_debug("Powering on fibre ports & reset\n");
-               rtl8380_sds_power(24, 1);
-               rtl8380_sds_power(26, 1);
-       }
-
        return 0;
 }
 
index b8c944425ed045e77c3919ac754042c0f95d58a3..66f4c6c148663e34a34b212aedfa9a5c7fee787f 100644 (file)
@@ -652,6 +652,7 @@ static struct phylink_pcs *rtldsa_phylink_mac_select_pcs(struct dsa_switch *ds,
        return priv->pcs[port];
 }
 
+__attribute__((unused))
 static void rtl83xx_config_interface(int port, phy_interface_t interface)
 {
        u32 old, int_shift, sds_shift;
@@ -754,7 +755,7 @@ static void rtl83xx_phylink_mac_config(struct dsa_switch *ds, int port,
        mcr = sw_r32(priv->r->mac_force_mode_ctrl(port));
        if (mode == MLO_AN_PHY || phylink_autoneg_inband(mode)) {
                pr_debug("port %d PHY autonegotiates\n", port);
-               rtl83xx_config_interface(port, state->interface);
+
                mcr |= RTL838X_NWAY_EN;
        } else {
                mcr &= ~RTL838X_NWAY_EN;
index fff84a3e8478fc8cc0c9ce62142a1f04d4dcc8f9..e41c89e71319b6bd80ee63a9f9bdf4e65b541741 100644 (file)
@@ -453,7 +453,6 @@ static int rtpcs_838x_sds_patch(struct rtpcs_ctrl *ctrl, u32 sds,
        return 0;
 }
 
-__always_unused
 static int rtpcs_838x_init_serdes_common(struct rtpcs_ctrl *ctrl)
 {
        u32 val;
@@ -474,7 +473,6 @@ static int rtpcs_838x_init_serdes_common(struct rtpcs_ctrl *ctrl)
        return 0;
 }
 
-__always_unused
 static int rtpcs_838x_setup_serdes(struct rtpcs_ctrl *ctrl, int sds,
                                   phy_interface_t mode)
 {
@@ -3101,6 +3099,8 @@ static const struct rtpcs_config rtpcs_838x_cfg = {
        .mac_rx_pause_sts       = RTPCS_838X_MAC_RX_PAUSE_STS,
        .mac_tx_pause_sts       = RTPCS_838X_MAC_TX_PAUSE_STS,
        .pcs_ops                = &rtpcs_838x_pcs_ops,
+       .init_serdes_common     = rtpcs_838x_init_serdes_common,
+       .setup_serdes           = rtpcs_838x_setup_serdes,
 };
 
 static const struct phylink_pcs_ops rtpcs_839x_pcs_ops = {
index fe72beded3e248c2e402dac2737a17d92d61af39..04b673e0c01f02d73dcc7104c4e332fdc38e6a24 100644 (file)
@@ -146,6 +146,7 @@ static void rtl8380_phy_reset(struct phy_device *phydev)
 /* Read the link and speed status of the 2 internal SGMII/1000Base-X
  * ports of the RTL838x SoCs
  */
+__attribute__((unused))
 static int rtl8380_read_status(struct phy_device *phydev)
 {
        int err;
@@ -1107,14 +1108,7 @@ static int rtl838x_serdes_probe(struct phy_device *phydev)
        if (addr < 24)
                return -ENODEV;
 
-       /* On the RTL8380M, PHYs 24-27 connect to the internal SerDes */
-       if (soc_info.id == 0x8380) {
-               if (addr == 24)
-                       return rtl8380_configure_serdes(phydev);
-               return 0;
-       }
-
-       return -ENODEV;
+       return 0;
 }
 
 static int rtl8393_serdes_probe(struct phy_device *phydev)